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authorB. Watson <yalhcru@gmail.com>2020-10-12 15:12:21 -0400
committerWilly Sudiarto Raharjo <willysr@slackbuilds.org>2020-10-17 09:37:38 +0700
commit9a5f389f295820c8b18b7b11672c83db4a007d37 (patch)
treed72f5cbfe60cbc23f9d28b460ac0de990c99ded7 /academic
parent2b82fc143294df8a7486a603ba4ce8dd2e5b137b (diff)
downloadslackbuilds-9a5f389f295820c8b18b7b11672c83db4a007d37.tar.gz
academic/verilog: Fix README.
Signed-off-by: B. Watson <yalhcru@gmail.com> Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'academic')
-rw-r--r--academic/verilog/README11
1 files changed, 6 insertions, 5 deletions
diff --git a/academic/verilog/README b/academic/verilog/README
index c8ebda2ee7..9df78abc32 100644
--- a/academic/verilog/README
+++ b/academic/verilog/README
@@ -1,5 +1,6 @@
-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
-a compiler, compiling source code written in Verilog (IEEE-1364) into some
-target format. For batch simulation, the compiler can generate an intermediate
-form called vvp assembly. This intermediate form is executed by the 'vvp'
-command. For synthesis, the compiler generates netlists in the desired format.
+Icarus Verilog is a Verilog simulation and synthesis tool. It operates
+as a compiler, compiling source code written in Verilog (IEEE-1364)
+into some target format. For batch simulation, the compiler can
+generate an intermediate form called vvp assembly. This intermediate
+form is executed by the 'vvp' command. For synthesis, the compiler
+generates netlists in the desired format.