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| -rw-r--r-- | academic/verilog/README | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/academic/verilog/README b/academic/verilog/README index c8ebda2ee7..9df78abc32 100644 --- a/academic/verilog/README +++ b/academic/verilog/README @@ -1,5 +1,6 @@ -Icarus Verilog is a Verilog simulation and synthesis tool. It operates as -a compiler, compiling source code written in Verilog (IEEE-1364) into some -target format. For batch simulation, the compiler can generate an intermediate -form called vvp assembly. This intermediate form is executed by the 'vvp' -command. For synthesis, the compiler generates netlists in the desired format. +Icarus Verilog is a Verilog simulation and synthesis tool. It operates +as a compiler, compiling source code written in Verilog (IEEE-1364) +into some target format. For batch simulation, the compiler can +generate an intermediate form called vvp assembly. This intermediate +form is executed by the 'vvp' command. For synthesis, the compiler +generates netlists in the desired format. |