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authorBrian Smith <brian@dbsoft.org>2023-09-17 06:21:49 -0500
committerBrian Smith <brian@dbsoft.org>2023-09-17 06:21:49 -0500
commit8f26f1a87321c47622bdeac2f610d31c33970b7e (patch)
treeabe0671ab068092e2d69fe8e79b8939b8ebfc68b /js
parent53ce8148585f74b2a4f9d9d3995e4a02e215e22b (diff)
downloaduxp-8f26f1a87321c47622bdeac2f610d31c33970b7e.tar.gz
Issue #2308 & #1240 Follow-up - Fill in missing JSOP_INC/DEC cases for Ion on Intel32/64.
Diffstat (limited to 'js')
-rw-r--r--js/src/jit/CodeGenerator.cpp2
-rw-r--r--js/src/jit/x64/SharedIC-x64.cpp10
-rw-r--r--js/src/jit/x86/SharedIC-x86.cpp11
3 files changed, 23 insertions, 0 deletions
diff --git a/js/src/jit/CodeGenerator.cpp b/js/src/jit/CodeGenerator.cpp
index 0459592448..5c2d9ac4e7 100644
--- a/js/src/jit/CodeGenerator.cpp
+++ b/js/src/jit/CodeGenerator.cpp
@@ -2378,6 +2378,8 @@ CodeGenerator::visitUnarySharedStub(LUnarySharedStub* lir)
switch (jsop) {
case JSOP_BITNOT:
case JSOP_NEG:
+ case JSOP_INC:
+ case JSOP_DEC:
emitSharedStub(ICStub::Kind::UnaryArith_Fallback, lir);
break;
case JSOP_CALLPROP:
diff --git a/js/src/jit/x64/SharedIC-x64.cpp b/js/src/jit/x64/SharedIC-x64.cpp
index 9e38cef6bf..ccad231d90 100644
--- a/js/src/jit/x64/SharedIC-x64.cpp
+++ b/js/src/jit/x64/SharedIC-x64.cpp
@@ -216,6 +216,16 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
masm.branchTest32(Assembler::Zero, R0.valueReg(), Imm32(0x7fffffff), &failure);
masm.negl(R0.valueReg());
break;
+ case JSOP_INC: {
+ RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.valueReg());
+ masm.inc32(&rval);
+ break;
+ }
+ case JSOP_DEC: {
+ RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.valueReg());
+ masm.dec32(&rval);
+ break;
+ }
default:
MOZ_CRASH("Unexpected op");
}
diff --git a/js/src/jit/x86/SharedIC-x86.cpp b/js/src/jit/x86/SharedIC-x86.cpp
index ee00e1bf0d..b293106ce3 100644
--- a/js/src/jit/x86/SharedIC-x86.cpp
+++ b/js/src/jit/x86/SharedIC-x86.cpp
@@ -226,6 +226,17 @@ ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
masm.branchTest32(Assembler::Zero, R0.payloadReg(), Imm32(0x7fffffff), &failure);
masm.negl(R0.payloadReg());
break;
+ case JSOP_INC: {
+ RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
+ masm.inc32(&rval);
+ break;
+ }
+ case JSOP_DEC: {
+ RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
+ masm.dec32(&rval);
+ break;
+ }
+
default:
MOZ_CRASH("Unexpected op");
}