From ab05ac3f2e155e5b8bcff71ba1499b28fa70f825 Mon Sep 17 00:00:00 2001 From: Charles Daniels Date: Fri, 20 Mar 2020 19:30:05 +0700 Subject: academic/verilator: Added (Verilog HDL Simulator). Signed-off-by: Willy Sudiarto Raharjo --- academic/verilator/slack-desc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 academic/verilator/slack-desc (limited to 'academic/verilator/slack-desc') diff --git a/academic/verilator/slack-desc b/academic/verilator/slack-desc new file mode 100644 index 0000000000..1bb74ecb6d --- /dev/null +++ b/academic/verilator/slack-desc @@ -0,0 +1,19 @@ +# HOW TO EDIT THIS FILE: +# The "handy ruler" below makes it easier to edit a package description. +# Line up the first '|' above the ':' following the base package name, and +# the '|' on the right side marks the last column you can put a character in. +# You must make exactly 11 lines for the formatting to be correct. It's also +# customary to leave one space after the ':' except on otherwise blank lines. + + |-----handy-ruler------------------------------------------------------| +verilator: verilator (the fastest free Verilog HDL simulator) +verilator: +verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. +verilator: It "Verilates" the specified synthesizable Verilog or SystemVerilog +verilator: code by reading it, performing lint checks, and optionally inserting +verilator: assertion checks and coverage-analysis points. It outputs single- or +verilator: multi-threaded .cpp and .h files, the "Verilated" code. +verilator: +verilator: homepage: https://www.veripool.org/wiki/verilator +verilator: +verilator: -- cgit v1.2.3