| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | academic/verilator: Added (Verilog HDL Simulator). | Charles Daniels | 2020-03-20 |
| Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org> | |||
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| slackbuilds.org: master branch [Local Fork] | khronosschoty@posteo.org |
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