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-rw-r--r--system/d52/tests/test.asm60
-rw-r--r--system/d52/tests/test.ctl125
-rw-r--r--system/d52/tests/test.d52102
-rw-r--r--system/d52/tests/test.hex4
4 files changed, 291 insertions, 0 deletions
diff --git a/system/d52/tests/test.asm b/system/d52/tests/test.asm
new file mode 100644
index 0000000000..7313e33c0f
--- /dev/null
+++ b/system/d52/tests/test.asm
@@ -0,0 +1,60 @@
+;
+; Test file for D52.
+; This, with the associated test.ctl file, demonstrates the
+; use of control file directives.
+;
+accum equ 0e0h
+;
+ org 0
+;
+start: nop
+ ajmp main
+ ljmp subrt
+;
+main: rr a
+ inc accum
+ inc 12h
+ inc @r0
+ inc @r1
+ inc r0
+ jbc acc.3,label
+ acall subrt
+ lcall subrt
+label: rrc a
+ dec a
+ dec 10h
+ dec @r0
+ dec @r1
+ dec r0
+ cjne a,#12h,label
+ mov dptr,#vectbl
+ jmp @a+dptr
+;
+subrt: nop
+ nop
+ nop
+ nop
+ nop
+ ret
+;
+vectbl: dw subrt
+ dw 0
+;
+mesg: db 'This is text',0
+;
+bindat: db 0,1,2,3
+wordat: dw 10h,20h,30h
+;
+; random junk to fake out the disassembler
+;
+ db 80h,29h,44h,33h
+;
+; valid code:
+;
+delay: mov r0,#5
+delay1: clr 20h
+ djnz r0,delay1
+ ret
+;
+ end
+;
diff --git a/system/d52/tests/test.ctl b/system/d52/tests/test.ctl
new file mode 100644
index 0000000000..1a6731b362
--- /dev/null
+++ b/system/d52/tests/test.ctl
@@ -0,0 +1,125 @@
+;
+; TEST.CTL - Sample Control File for D52
+;
+; Control codes allowed in the CTL file:
+;
+; A - Address Specifies that the word entry is the address of
+; something for which a label should be generated.
+;
+; B - Byte binary Eight bit binary data (db).
+;
+; C - Code Executable code that must be analyzed.
+;
+; F - SFR label Specify name for SFR.
+;
+; I - Ignore Treat as uninitialized space. Will not be dis-
+; assembled as anything unless some other valid
+; code reaches it.
+;
+; K - SFR bit Specify name for SFR bit.
+;
+; L - Label Generate a label for this address.
+;
+; M - Memory Generate a label for bit addressable memory.
+;
+; P - Patch Add inline code (macro, for example)
+;
+; R - Register Specify name for register
+; (instead of rb2r5 for example).
+;
+; S - Symbol Generate a symbol for this value.
+;
+; T - Text ASCII text (db).
+;
+; W - Word binary Sixteen bit binary data (dw).
+;
+; X - Operand name Specify special name for operand.
+;
+; # - Comment Add header comment to output file.
+;
+; ! - Inline comment Add comment to end of line.
+;
+; example labels:
+;
+l 0000 start
+l 0006 main
+l 0016 loop
+l 0024 subrtn
+l 002a vectbl
+l 002e message
+;
+; example symbol:
+;
+s 12 counter
+;
+; example ascii text:
+;
+t 002e-003a
+;
+; example register names:
+;
+r 10 reg0
+r 12 reg2
+;
+; example SFR name:
+;
+f e0 accum
+;
+; example SFR bit name:
+;
+k e3 abit3
+;
+; example memory bit name:
+;
+m 20 membit
+;
+; example operand name:
+;
+x 004a five
+;
+; example header comments:
+;
+# 0024 This is a subroutine.\n
+# 002e 't' directive for ascii text\n
+# 003b \nData - 'b' and 'w' directives\n
+# 003f
+;
+; example inline comments:
+;
+! 0007 note sfr bit def only affects indirect addressing
+! 001d do the loop
+! 0024 do nothing routine
+! 0025 these nops would not be disassembled
+! 0026 without the 'c' directive
+! 003b binary data
+! 003f word data
+# 0049 would get junk from 45h to 48h if not for the 'i' directive\n
+! 0049 example of operand name 'x' directive
+! 004b 'm' bit addressable memory directive
+;
+; example address table:
+;
+a 002a-002d
+;
+; example force disassembly of code (nops):
+;
+c 0025-0029
+;
+; example code to ignore:
+;
+i 0045-0048
+;
+; example binary data:
+;
+b 003b-003e
+;
+; example word data:
+;
+w 003f-0044
+;
+; example patch code:
+;
+p 0003 include "myfile.inc"\n;
+;
+; end of control file
+;
diff --git a/system/d52/tests/test.d52 b/system/d52/tests/test.d52
new file mode 100644
index 0000000000..3809b2be2b
--- /dev/null
+++ b/system/d52/tests/test.d52
@@ -0,0 +1,102 @@
+;
+; D52 V3.3.6 8052 Disassembly of test.hex
+; 01/23/05 12:15
+;
+ org 0
+;
+start: nop ; 0000 00 .
+ ajmp main ; 0001 01 06 ..
+;
+ include "myfile.inc"
+;
+ ljmp subrtn ; 0003 02 00 24 ..$
+;
+main: rr a ; 0006 03 .
+ inc accum ; 0007 05 e0 .` ; note sfr bit def only affects indirect addressing
+ inc reg2 ; 0009 05 12 ..
+ inc @r0 ; 000b 06 .
+ inc @r1 ; 000c 07 .
+ inc r0 ; 000d 08 .
+ jbc abit3,loop ; 000e 10 e3 05 .c.
+ acall subrtn ; 0011 11 24 .$
+ lcall subrtn ; 0013 12 00 24 ..$
+loop: rrc a ; 0016 13 .
+ dec a ; 0017 14 .
+ dec reg0 ; 0018 15 10 ..
+ dec @r0 ; 001a 16 .
+ dec @r1 ; 001b 17 .
+ dec r0 ; 001c 18 .
+ cjne a,#counter,loop ; 001d b4 12 f6 4.v ; do the loop
+ mov dptr,#vectbl ; 0020 90 00 2a ..*
+ jmp @a+dptr ; 0023 73 s
+;
+; This is a subroutine.
+;
+subrtn: nop ; 0024 00 . ; do nothing routine
+ nop ; 0025 00 . ; these nops would not be disassembled
+ nop ; 0026 00 . ; without the 'c' directive
+ nop ; 0027 00 .
+ nop ; 0028 00 .
+ ret ; 0029 22 "
+;
+vectbl: dw subrtn ; 002a 00 24 .$
+ dw start ; 002c 00 00 ..
+;
+; 't' directive for ascii text
+;
+message: db 'This is text' ; 002e
+ db 0 ; 003a .
+;
+; Data - 'b' and 'w' directives
+;
+ db 0 ; 003b . ; binary data
+ db 1,2,3 ; 003c ...
+;
+ dw 10h ; 003f 00 10 .. ; word data
+ dw 20h ; 0041 00 20 .
+ dw 30h ; 0043 00 30 .0
+;
+;
+; would get junk from 45h to 48h if not for the 'i' directive
+;
+ org 49h
+;
+ mov r0,#five ; 0049 78 05 x. ; example of operand name 'x' directive
+X004b: clr membit ; 004b c2 20 B ; 'm' bit addressable memory directive
+ djnz r0,X004b ; 004d d8 fc X|
+ ret ; 004f 22 "
+;
+; Register/Memory Equates
+;
+reg0 equ 10h
+reg2 equ 12h
+;
+; SFR Equates
+;
+accum equ 0e0h
+;
+; SFR bit Equates
+;
+abit3 equ 0e3h
+;
+; Memory bit Equates
+;
+membit equ 20h
+;
+; Symbol equates
+;
+; These are symbols from the control
+; file that are referenced in the code
+;
+counter equ 12h
+;
+; Operand symbol equates
+;
+; These are operand symbols from the control
+; file that are referenced in the code
+;
+five equ 5
+;
+ end
+;
+
diff --git a/system/d52/tests/test.hex b/system/d52/tests/test.hex
new file mode 100644
index 0000000000..ade6d93051
--- /dev/null
+++ b/system/d52/tests/test.hex
@@ -0,0 +1,4 @@
+:200000000001060200240305E0051206070810E305112412002413141510161718B412F6EF
+:2000200090002A7300000000002200240000546869732069732074657874000001020300CE
+:100040001000200030802944337805C220D8FC22DB
+:00005001AF