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| author | Stephen Van Berg <stephen_van_berg@earlicker.com> | 2010-05-13 00:57:23 +0200 |
|---|---|---|
| committer | Robby Workman <rworkman@slackbuilds.org> | 2010-05-13 00:57:23 +0200 |
| commit | da95dc10a47511570a1726efa28789d94bf23a3f (patch) | |
| tree | 8e940a145d9b0d04143ce73b0aab3e593290b0c4 /academic/verilog/README | |
| parent | f334d6acba797cac07b34bcb7e016ccf2267dbba (diff) | |
| download | slackbuilds-da95dc10a47511570a1726efa28789d94bf23a3f.tar.gz | |
academic/verilog: Added to 13.0 repository
Diffstat (limited to 'academic/verilog/README')
| -rw-r--r-- | academic/verilog/README | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/academic/verilog/README b/academic/verilog/README new file mode 100644 index 0000000000..c8ebda2ee7 --- /dev/null +++ b/academic/verilog/README @@ -0,0 +1,5 @@ +Icarus Verilog is a Verilog simulation and synthesis tool. It operates as +a compiler, compiling source code written in Verilog (IEEE-1364) into some +target format. For batch simulation, the compiler can generate an intermediate +form called vvp assembly. This intermediate form is executed by the 'vvp' +command. For synthesis, the compiler generates netlists in the desired format. |