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| author | Charles Daniels <charles [at] cdaniels [dot] net> | 2020-03-20 19:30:05 +0700 |
|---|---|---|
| committer | Willy Sudiarto Raharjo <willysr@slackbuilds.org> | 2020-03-20 19:30:05 +0700 |
| commit | ab05ac3f2e155e5b8bcff71ba1499b28fa70f825 (patch) | |
| tree | 4320c3f751a71ae6c05d377c000b3d73f3e18113 /academic/units/README | |
| parent | f6bf1970803b476ceb857e28e8b7b1bcce7c01b0 (diff) | |
| download | slackbuilds-ab05ac3f2e155e5b8bcff71ba1499b28fa70f825.tar.gz | |
academic/verilator: Added (Verilog HDL Simulator).
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'academic/units/README')
0 files changed, 0 insertions, 0 deletions